In recent years, the downsizing and performance-enhancement of electronic instruments or machines such as cellphones, notebook computers, liquid crystal televisions, etc., are proceeding at a rapid pace. For making these electronic instruments or machines, there are employed techniques such as wiring formation of internal printed circuit boards (PCB), wafer level package (WLP) and micro electro mechanical system (MEMS) package, three-dimensional stacking technique, etc. There is an electroplating method employed for buildup substrates which are printed circuit boards or multilayer-structured printed circuit boards among substrates to which the above wiring formation is applied, and it is a via filling technology.
The electroplating method has an advantage that the cost therefor is low since it uses a simple apparatus as compared with a vacuum vapor deposition method. Further, copper has excellent metallic properties that it has high electric conductivity and heat dissipation property, and it can be said to be a metal material suitable for connection of the wiring formation. For the wiring formation of the above printed circuit board, etc., there is used the technique of hole-plugging plating.
In the via filling technology, when buildup substrates are stacked as package substrates inside a device, desirably, a plating layer is deposited as a layer that is as thin as possible and as smooth as possible outside a non-through hole such as a via hole (fine hole) or a trench (fine groove) (that is, a plating-inhibiting effect is desirable) for facilitating chemical mechanical polishing (CMP). On the other hand, a bottom portion of the non-through hole is required to be brought into a state where it is fully filled with a deposited plating by the promotion of deposition of a plating for securing high conductivity. That is, it is preferred to produce a plating promotion effect for causing no void (see Non-Patent Document 1).
In the via filling technology, these contradicting plating effects are required for plating the bottom and outer portion of a non-through hole as described above, so that a plating bath to be used is required to contain four additives having various effects in addition to a basic composition containing copper sulfate and sulfuric acid (see Patent Documents 1˜3). As the above additives, four additives of a brightener, a carrier, a leveler and chloride ion are known.
The brightener is a plating promoter, and includes organic sulfur compounds such as bissulfoalkane sulfonate, sulfoalkyl sulfonate, a dithiocarbamic acid derivative, bis-(sulfoalkyl)disulfide salt, etc.
The carrier is a plating inhibitor that is adsorbed on a copper surface to inhibit an electro deposition reaction, and it includes polyethylene glycol, polypropylene glycol, a copolymer of ethylene glycol and propylene glycol, etc.
The leveler is a plating inhibitor that is adsorbed on a copper surface to inhibit electro deposition like the carrier. It includes thiourea, benzotriazole, poly(N-vinyl-N-methylimidazolium chloride), poly(N-vinylpyrolidone), poly(diallyldimethylammonium chloride), Janus green•B, etc.
The chloride ion works to promote anode dissolution and inhibit the occurrence of anode slime.
However, when a plurality of these additives are co-present in the plating bath, the additives are consumed in different proportions as the plating is carried out, so that the amount ratio of the additives in the plating bath changes with time. In the via filling technology using a plating bath containing a plurality of additives, therefore, it is difficult to maintain the plating layer properties and plugging property at constant level, and there is involved a problem that it requires complicated formulation of the additives and troublesome control of concentrations to overcome the above situation (see Patent Document 4).
[Prior Art Documents]
                [Non-Patent Documents]        [Non-Patent Document 1]        
Fujikura Technical Review, Vol, 108, pages 31-34                [Patent Documents]        [Patent Document 1]        
JP 2001-200386 A                [Patent Document 2]        
JP 2005-29818 A                [Patent Document 3]        
JP 2007-138265 A                [Patent Document 4]        
JP 2001-73183 A